Correcting multiple design errors in digital VLSI circuits

نویسندگان

  • Andreas G. Veneris
  • Ibrahim N. Hajj
چکیده

Andreas G.Veneris University of Illinois at Urbana-Champaign Department of Computer Science e-mail: [email protected] Ibrahim N.Hajj University of Illinois at Urbana-Champaign Department of Electrical and Computer Engineering e-mail: [email protected] Abstract With the increase in the complexity of VLSI circuit design, logic design errors can occur during the synthesis process. In this paper we present an e cient test{vector simulation approach for multiple design error diagnosis and correction. We also compare the quality of test vector simulation and BDDs for this problem and show the competitive performance of the former. Experimental results exhibit the robustness of our approach and con rm the theoretical results.

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تاریخ انتشار 1999